A method of manufacturing a semiconductor device usingsimplified processing and eliminating and/or minimizing theextrinsic parasitic elements of the device. The method isparticularly suited for manufacturing heterojunction bipolartransistors where the extrinsic parasitic base resistance and theextrinsic parasitic base-collector and base-emitter capacitancescan be virtually eliminated and the base contact resistance can begreatly reduced. The method includes formming symmetric emitter andcollector portions using front and backside processing of thewafer, respectively. The symmetric emitter and collector virtuallyeliminates the extrinsic collector and emitter regions of thedevice thereby virtually eliminating the extrinsic base-collectorand base-emitter capacitance. The extrinsic base contact region mayalso be increased to minimize the base contact resistance withoutincreasing parasitic capacitive elements of the device.Self-aligned processing features are also included to formself-aligned contacts to the base layer thereby virtuallyeliminating the extrinsic base resistance. The method may includebuilding up the collector and emitter contacts to separate theemitter and collector interconnections from the base layer to avoidincreasing the emitter-base and collector-base extrinsic parasiticcapacitances and to minimize associated resistances andinductances. The method may further include forming etch stoplayers to facilitate removing of the substrate to perform thebackside processing and to accurately etch through the collectorlayer without etching the base layer.
Symmetric self-aligned processing
Enquist, P., & Slater, DB. (1994). IPC No. U.S. Symmetric self-aligned processing. (U.S. Patent No. 5318916).