Bump interconnect for 2.5D and 3D integration
Huffman, C. (2014). Bump interconnect for 2.5D and 3D integration. In P. Garrou, M. Koyanagi, & P. Ramm (Eds.), Handbook fo 3D Integration: 3D Process Technology. Vol. 3 (pp. 313-323). Weinheim, Germany: Wiley-VCH.
The use of bump interconnects in the electronic packaging is not ubiquitous. As 3D integration technologies were first being envisioned, bump interconnects were always seen as one of the primary methods for interconnecting devices. Bump interconnects provide short connection lengths, low parasitics, and high mechanical stability - all of which are needed for 3D systems. More recently, the term 2.5D has been used to describe the use of silicon and glass as substrate materials that provide a platform for integrating devices. 2.5D technologies offer the ability to integrate devices with fine-line interconnects and the vertical interconnections can be placed in the substrate, simplifying processing and reducing the risk to ICs. As 2.5D/3D technology has been evolving, bump interconnects have continued to advance as well, with higher interconnect densities and ever smaller dimensions. The widespread acceptance of 2.5D and 3D integration is ushering in the next paradigm change in electronic packaging, and bump interconnects play an important role in the evolution of this technology. This chapter will take an in-depth look at various bump technologies, their evolution, and their application to 2.5D and 3D techology.