Enabling more capability within smaller pixels

Over the past decade, the development of infrared focal plane arrays (FPAs) has seen two trends: decreasing of the pixel size and increasing of signal-processing capability at the device level. Enabling more capability within smaller pixels can be achieved through the use of advanced wafer-level processes for the integration of FPAs with silicon (Si) readout integrated circuits (ROICs). In this paper, we review the development of these wafer-level integration technologies, highlighting approaches in which the infrared sensor is integrated with three-dimensional ROIC stacks composed of multiple layers of Si circuitry interconnected using metal-filled through-silicon vias.