Historically, building larger imaging/display arrays has been based on increasing the size of the read-out IC (ROIC) or read-in IC (RIIC) for imaging and display applications, respectively. However, the ROIC/RIIC die yield is inversely proportional to the die size, with IC die yields decreasing exponentially as die sizes exceed one inch square. As a result, the imaging/display communities need a much better approach for realizing large imaging/display formats.
Decreasing Chip Gaps without Compromising Detection or Scene Integrity
One potential solution is to tile smaller, higher-yielding IC die to build larger overall imaging/display systems. However, for these applications, the gap between tiled chips must be less than half the pitch of a pixel to ensure no loss of detection (or bearing) as the item being sensed or projected moves across the seams between chips. This puts the desired gap between chips at ≤ 10 um.
Enabling Tiling of Higher-Yielding, Small IC Chips for Use in Arrays and Optical Systems
Using Quilt Packaging technology, our team has worked with Indiana Integrated Circuits and Santa Barbara Infrared, Inc., to successfully demonstrate sub-10-um chip gaps with sub-micron alignment accuracy between chips.
This demonstration also showed the compatibility of the quilt packaging fabrication and assembly processes with TSVs (in this case, unfilled TSVs). This project, which was funded by the Department of Defense, proved the feasibility of using the Quilt Packaging technology for building large imaging/display arrays and for optical systems requiring precision alignment between chips.