RESEARCH TRIANGLE PARK, N.C. — A new book, "Handbook of 3D Integration: Volume 3- 3D Process Technology," provides an in-depth description of the complex details of 3D process technology.
Three RTI International researchers contributed to the volume, published by Wiley. The book serves as a valuable text for semiconductor industry professionals, including: researchers, designers, engineers, managers, and equipment manufacturers.
"3D integration is a leading edge chip stacking technique, which is expected to become the forefront packaging technology for integrated circuits in high end computers and mobile devices," said Phil Garrou, co-editor of the book. "The previous two volumes of the book are the most referenced 3D handbooks in the industry."
Three-dimensional integration involves stacking electronic chips upward to minimize size instead of just making the chip area smaller. Stacking the chips allows devices to be smaller and lighter, use less power, and achieve higher performance.
The book describes the latest advances in process technology for silicon via formation, temporary bonding and debonding, wafer thinning, via reveal and backside processing, and 3D assembly. The book also includes information about assessing and enhancing the reliability of 3D integrated devices, which is a requirement for large-scale implementation of this technology.
"RTI was honored to have 3 staff members invited to contribute chapters to this important technology book, along with research and industry experts from around the world," said Dean Malta, engineering manager of 3D integration at RTI and contributing author of the book. "We have been actively developing leading edge 3D integration technologies for nearly 15 years. RTI is working with a variety of government and commercial clients to develop 3D technology solutions for defense, communications, high performance computing, and other emerging applications."
Malta authored a chapter titled, "TSV Formation Overview," which examines the processing of through silicon vias (TSVs) in integrated circuit wafers for 3D integration, or in silicon interposer wafers for 2.5D advanced package architectures. The chapter includes a review of possible TSV process approaches, TSV fabrication process steps and challenges, and potential reliability issues.
Alan Huffman, engineering manager of wafer level packaging at RTI, wrote a chapter titled "Bump Interconnect for 2.5D and 3D Integration." The chapter describes how different bump structures are used to connect components in 2.5 and 3D systems, explains the varying structures, materials and dimensions of bump interconnects used in 2.5/3D packaging architectures, and discusses their relative advantages and disadvantages.
Matthew Lueck, research engineer at RTI, authored a chapter titled "Comparison of Temporary Bonding and Debonding Process Flows," which provides an overview of research conducted by RTI and other organizations to compare the different types of temporary wafer bonding carriers. Temporary wafer bonding carriers are used to support thinned wafers during the fabrication of 3D integrated circuits.
As a leader in 3D integration and through-silicon via (TSV) technology, RTI has developed a wide range of process capabilities and achieved successful demonstrations of 3D integrated circuit (3D-IC) stacks, advanced silicon interposer substrates, and 3D passive structures. RTI has been conducting research and development in 3D integration since 1999, building on decades of prior experience in the development of advanced packaging and microfabrication technologies.
The "Handbook of 3D Integration: Volume 3- 3D Process Technology" is available on leading commercial bookseller websites.