Sub-arrays such as tiles or chips having pixel elements arranged on a routing layer or carrier to form a larger array. Through-chip vias or the like to the backside of the chip are used for connecting with the pixel elements. Edge features of the tiles may provide for physical alignment, mechanical attachment and chip-to-chip communication. Edge damage tolerance with minimal loss of function may be achieved by moving unit cell circuitry and the electrically active portions of a pixel element away from the tile edge(s) while leaving the optically active portion closer to the edge(s) if minor damage will not cause a complete failure of the pixel. The pixel elements may be thermal emitter elements for IR image projectors, thermal detector elements for microbolometers, LED-based emitters, or quantum photon detectors such as those found in visible, infrared and ultraviolet FPAs (focal plane arrays), and the like. Various architectures are disclosed.
Techniques for Tiling Arrays of Pixel Elements
LaVeigne, JD., Lannon, J., Goodwin, S., & Kulick, J. (2015). IPC No. U.S. Techniques for Tiling Arrays of Pixel Elements. (U.S. Patent No. 9163995).