A semiconductor device and method of fabricating the device. Anemitter region is formed self centered and self alignedsymmetrically with a base region. Using frontside processingtechniques, a collector is formed symmetrically self-aligned withthe base region and the emitter region. The collector region may befurther formed self-centered with the base region using backsideprocessing techniques. The self-aligned and self-centered symmetricstructure virtually eliminates parasitic elements in the devicesignificantly improving the device performance. The device isscalable on the order of approximately 0.1 microns. The method alsoprovides reproduceability and repeatability of devicecharacteristics necessary for commercial manufacture of thesymmetric device.
Self aligned symmetric process and device
Enquist, P. (2002). IPC No. U.S. Self aligned symmetric process and device. (U.S. Patent No. 6368930).