A differential built-in current sensor design for high-speed IDDQ testing
A new built-in current sensor design for IDDQ testing is presented in this paper. Our design overcomes performance limitations encountered by previous sensors by using a novel differential architecture which allows early and accurate detection of abnormal quiescent current following the switching transient. This differential design also naturally compensates for inaccuracies due to any build up of leakage currents and subthreshold conduction effects when relatively large circuit partitions are tested. A test circuit utilizing the sensor in a built-in self-test environment has been fabricated. At clock speeds of up to 31.25 MHz the sensor accurately detects all six of the defects that were implanted in the test chip. SPICE3 simulations of the circuit indicate that with careful design, this sensor can accurately detect faults at operational speeds in a variety of situations.
Hurst, J., & Singh, AD. (1997). A differential built-in current sensor design for high-speed IDDQ testing. IEEE Journal of Solid-State Circuits, 32(1), 122-125. https://doi.org/10.1109/4.553192