Demonstration of low cost TSV fabrication in thick silicon wafers
Vick, E., Temple, D. S., Anderson, R., Lannon, J., Li, C., Peterson, K., ... Han, C. J. (2014). Demonstration of low cost TSV fabrication in thick silicon wafers. In In Electronic Components and Technology Conference (ECTC), 2014 IEEE 64th, 27-30 May 2014, Orlando, FL, pp. 1641–1647. .
Low cost wafer-level chip-scale vacuum packaging (WLCSVP) imposes unique constraints on potential implementation of through-silicon vias (TSVs). A WLCSVP requires a relatively thick substrate to prevent mechanical failure. Two approaches for integrating TSVs in thick silicon wafers have been successfully demonstrated. Both approaches enable TSV formation from the backside of a device wafer and are compatible with the requirements of subsequent packaging operations. We achieved low contact resistance between TSVs and frontside Ti/Cu and Al metallization, while demonstrating high isolation resistance and high TSV yield.