Engineering control of nanostructures is becoming increasingly important as nanotechnology applications develop and as device features shrink. In many nanotechnology-driven applications, bottoms-up fabrication of devices offers many inherent advantages over conventional top-down approaches typically employed today. In order to be commercially viable, bottoms-up fabrication methodologies must rely upon the synthesis and assembly of nanoengineered structures. The silicon nanoparticle-based floating-gate metal-oxide-semiconductor field effect transistor is an example of a device that incorporates nanostructures and is an attractive candidate for terabit cm?2 density nonvolatile memory applications. However, variability in the size, location, and interface electronic quality of the nanoparticles in an ensemble limits device performance. To reduce device variability, the Si nanoparticle layer can be fabricated using a bottoms-up approach. Aerosol Si nanoparticles are synthesized by thermal decomposition of silane gas in a reactor optimized to produce spherical, single-crystal, nonagglomerated nanoparticles. The aerosol nanoparticles are size-classified with a differential mobility analyzer to produce narrow size distributions. Uniform oxide layers in the nanometer thickness range are then formed on the Si nanoparticles, either by thermal oxidation or by aerosol vapor phase tetraethylorthosilicate deposition. Electronic measurements indicate that high temperature thermal SiO2 and deposited tetraethylorthosilicate-derived SiO2 form shells of sufficient quality and thickness to isolate electrically adjacent nanoparticles from each other. Photoluminescence measurements used to probe the Si/SiO2 interface indicate the presence of a high quality interface between deposited tetraethylorthosilicate oxide and Si nanoparticles.