Process integration and testing of TSV Si interposers for 3D integration applications

Scott H. Goodwin; Charles A. Huffman; John M. Lannon; Dean M. Malta; Dorota S. Temple; Erik P. Vick; Matthew R. Lueck; Christopher W. Gregory; Jeffery Allan Hilton; Garry Brian Cunningham; John M. Lannon; Jeffery Allan Hilton; Charles Alan Huffman; Matthew R. Lueck; Erik P. Vick; Scott H. Goodwin; Garry Brian Cunningham; Dean M. Malta; Christopher W. Gregory; Dorota S. Temple

Process integration and testing of TSV Si interposers for 3D integration applications

Lannon, J., Hilton, J., Huffman, C., Lueck, M., Vick, E., Goodwin, S., Cunningham, G., Malta, D., Gregory, C., & Temple, D. (2012). Process integration and testing of TSV Si interposers for 3D integration applications. In 2012 IEEE 62nd Electronic Components and Technology Conference (ECTC 2012), San Diego, CA, May 29-June 1, 2012 (pp. 268-273) https://doi.org/10.1109/ECTC.2012.6248839

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Abstract

Two 3D Si interposer demonstration vehicles containing through-Si vias (TSVs) were successfully fabricated using integration of two different TSV formation and multilevel metallization (MLM) process modules. The first Si interposer vehicles were made with a dual damascene frontside MLM (5 levels), backside TSV (unfilled, vias-last), and backside metallization (2 levels) process sequence on standard thickness 6” wafers. The front-side MLM was comprised of 4 metal routing layers (2 ?m Cu with 2 ?m oxide interlayer dielectric) and 1 metal pad layer. Electrical yield as high as 100% was obtained on contact chain test structures containing 26,400 vias between the front-side MLM layers, while the average contact resistance between the dual damascene levels was <; 4 M? per via. TSV dimensions of 100 and 80 ?m diameter and 6:1 aspect ratio were investigated. DRIE bottom clear process conditions were optimized for each via dimension to produce 100% yield on TSV contact chains with up to 540 vias. The optimized DRIE conditions also resulted in TSV resistance below 30 M? and sufficient TSV isolation resistance (>;100M?/via at 3.3V) for the target application. Functional testing of two die (4 cm × 3.7 cm die size) showed that 99% of the functional circuit path nets had acceptable continuity and isolation. The second Si interposer vehicles were fabricated using a vias-first TSV (filled, blind vias), wafer-level packaging (WLP) front-side MLM (2 levels), wafer thinning (via reveal), and WLP-MLM (1 level) process sequence on stock 6” wafers. Via dimensions for the viasfirst interposers were 50 ?m diameter × 315 ?m depth or 80 ?m diameter × 315 ?m depth (6:1 or 4:1 aspect ratios). The front and backside MLM was formed with a 2 ?m Cu routing layer and one of two spin-on dielectrics (polyimide or ALX) for evaluation of polymer dielectric process com- atibility with Cu-filled TSVs and thinned wafer processing. Details of the process modules and process integration required to realize the TSV Si interposers are described.