A three-dimensional interconnect includes a first substrate bonded to a second substrate, the first substrate including a device layer and a bulk semiconductor layer, a metal pad disposed on the second substrate, an electrically insulating layer disposed between the first and second substrates. The structure has a via-hole extending through the device layer, the bulk semiconductor layer and the electrically insulating layer to the metal pad on the second substrate. The structure has a dielectric coating on a sidewall of the via-hole, and a plasma-treated region of the metal pad disposed on the second substrate. The structure includes a via metal monolithically extending from the plasma-treated region of the metal pad through the via-hole and electrically interconnecting the device layer of the first substrate to the metal pad of the second substrate.
Three dimensional interconnect structure and method thereof
Williams, C., Bower, CA., Malta, D., & Temple, D. (2015). IPC No. U.S. Three dimensional interconnect structure and method thereof. (U.S. Patent No. 8975753). http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=8975753