Scaling of three-dimensional interconnect technology incorporating low temperature bonds to pitches of 10 µm for infrared focal plane array applications
This paper focuses on the application of low temperature bonding to the fabrication of three-dimensional (3D) massively parallel signal processors for high performance infrared imagers. We review two generations of the 3D heterogeneous integration process. The first generation process, compatible with pixel sizes in the 20 to 30 µm range, relies on low temperature epoxy bonding that is followed by the formation of copper-filled through-silicon vias (TSVs). The second generation process, scalable to pixel sizes of 10 µm and smaller, employs solid–liquid diffusion bonding of copper–tin to copper at 250 °C; the bonding follows TSV fabrication. To demonstrate the second generation process, we fabricated 3D test vehicles in the form of 640 × 512 arrays of vertical interconnects composed of TSVs and metal–metal bonds on a 10 µm pitch. We characterized electrical conductivity of the interconnects, the isolation resistance between the interconnects, and the operability and yield of the arrays. The successful demonstration of the interconnect technology paves the way to a functional demonstration of 3D signal processors in infrared imagers with 10 µm pixels.
Temple, D., Lueck, M., Malta, D., & Vick, E. (2015). Scaling of three-dimensional interconnect technology incorporating low temperature bonds to pitches of 10 µm for infrared focal plane array applications. Japanese Journal of Applied Physics, 54(3), 030202. https://doi.org/10.7567/JJAP.54.030202