High-density area-array 3-D interconnects are a key enabling technology for 3-D integrated circuits. This paper presents results of the fabrication and testing of large 640 by 512 area arrays of Cu/Sn-Cu interconnects positioned on 10-? centers. The processes used to create the interconnects are designed to be compatible with CMOS wafer requirements. Through testing of the electrical continuity of long chains of interconnects, bond yield is estimated to be greater than 99.99% in the large arrays. The properties of Cu/Sn-Cu interconnects remain stable through exposure to thermal cycling and high-humidity testing. For applications that have a low thermal budget, bonding of Cu/Sn-Cu at 250 °Cand at 210 °C, below the melting point of Sn, is demonstrated to produce similarly high yield and alloy composition as the higher temperature bonds.
High-density large-area-array interconnects formed by low-temperature Cu/Sn–Cu bonding for three-dimensional integrated circuits
Lueck, M., Reed, JD., Gregory, C., Huffman, C., Lannon, J., & Temple, D. (2012). High-density large-area-array interconnects formed by low-temperature Cu/Sn–Cu bonding for three-dimensional integrated circuits. IEEE Transactions on Electron Devices, 59(7), 1941-1947. https://doi.org/10.1109/TED.2012.2193404