• Conference Proceeding

Enabling more capability within smaller pixels: Advanced wafer-level process technologies for integration of focal plane arrays with readout electronics

Citation

Temple, D. S., Vick, E. P., Lueck, M. R., Malta, D., Skokan, M. R., Masterjohn, C. M., & Muzilla, M. S. (2014). Enabling more capability within smaller pixels: Advanced wafer-level process technologies for integration of focal plane arrays with readout electronics. In Image Sensing Technologies: Materials, Devices, Systems, and Applications, [91000], p. 91000L. .

Abstract

Over the past decade, the development of infrared focal plane arrays (FPAs) has seen two trends: decreasing of the pixel size and increasing of signal-processing capability at the device level. Enabling more capability within smaller pixels can be achieved through the use of advanced wafer-level processes for the integration of FPAs with silicon (Si) readout integrated circuits (ROICs). In this paper, we review the development of these wafer-level integration technologies, highlighting approaches in which the infrared sensor is integrated with three-dimensional ROIC stacks composed of multiple layers of Si circuitry interconnected using metal-filled through-silicon vias.