Post-CMOS Wafer Processing
RTI is a leader in the research and development of innovative materials, microstructures, and devices for microsystem integration and packaging. Our extensive experience in back-end-of-line processing makes us an ideal partner for the development or implementation of post-CMOS (complementary metal oxide semiconductor) wafer processes in
- Multi-level metallization
- High-density metal-metal interconnects for 3D integration
- Monolithic device integration
Our fully integrated fabrication and analytical facilities, combined with an experienced staff of full-time engineers and researchers, allow us to support a diverse project base developing new technologies and solutions for our clients.
Multi-Level Metallization
We develop and implement multi-level metallization schemes for applications such as high-power signal routing layers for read-in ICs and high-performance computing. We have employed shemes using inorganic dielectrics, organic dielectrics, or a combination of both inorganic and organic dielectrics for the interlayer dielectric.
High-Density Metal-Metal Interconnects for 3D Integration
As 3D integration technology becomes more prevalent, new methods of interconnecting devices with even smaller I/O pitches are required to support the unprecedented interconnect density. We are developing metal-metal bonding interconnect technologies for 3D integration that use arrays of copper and copper-tin pads. Our interconnect structures can be applied to most IC wafers for high I/O density interconnection, chip stacking for 3D integration, Si-to-Si integration, and applications requiring thermal and mechanical stability at temperatures beyond that of typical solder materials.
Monolithic Device Integration
We can fabricate device structures directly on IC or passive substrate wafers. We can work collaboratively with you and your customers to transfer technologies and/or develop designs and processes for monolithic integration of structures. Since 2002, we have been fabricating pixilated, suspended bridge structures on IC wafers for an infrared scene projector application. Through continued process modifications and materials development with the customer, we have improved pixel performance and yield while enhancing our process and design knowledge for other monolithic device integration applications.
Brochures
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- John M. Lannon