Advanced Interconnect and Packaging Technologies

RTI is home to one of the premier wafer bumping and wafer-level packaging research and fabrication facilities in the U.S. Our experts in material and electronic technologies have over 15 years of research, development, and implementation experience in all areas of bump interconnect technologies. From material characterization, to prototype and proof-of-concept, to pilot-line and small-scale production, we tailor our capabilities to meet each client's unique requirements.

Capabilities

Solder bumping and wafer-level chip-scale packaging
- Bump on I/O pad
- Bump on polymer
- Polymer repassivation
- Single and multiple layer redistribution
- Eutectic Sn/Pb, Pb-free, and Cu pillar bumping
- Design services
Electronic material characterization and process development
- Basic characterization
- Process parameterization
- Full implementation into WLP structures
- Reliability testing
- Analysis
Ultra-fine pitch flip chip bumping
Flip chip and multi-chip module assembly
- Single chip placements
- Multi-chip module and system-in-package assembly of multiple die and components
- RTI-patented plasma-assisted dry soldering (PADS) process
Metal-metal bonding for 3D integration
- High I/O density interconnection
- Chip stacking for 3D integration
- Si-to-Si integration
- Applications requiring thermal and mechanical stability at high solder temperatures

Brochures